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| PRODUCT SPECIFICATION Z89223/273/323/373 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER FEATURES Device Z89223 Z89273 Z89323 Z89373 Package 44-PLCC, 44-PQFP 44-PLCC 64-TQFP, 68-PLCC, 80-PQFP 64-TQFP, 68-PLCC, 80-PQFP ROM (Kwords) 8 8 8 8 OTP (Kwords) Data RAM (Words) 512 512 512 512 MIPS 20 20 20 20 Operating Range * * On-Chip Peripherals * * * 5V 10% 0C to 70C Standard Temperature -40C to +85C Extended Temperature 4-Channel, 8-Bit Half-Flash A/D Converter Serial Peripheral Interface (SPI) Three General-Purpose Counter/Timers - Two Pulse Width Modulators (PWM) - Two Watch-Dog Timers (WDT) Up to 40 Bits of I/O PLL System Clock Three Vectored Interrupts Servicing Eight Sources Low Power Clock Modes with Wake-up Options DSP Core * * * * * 16-Bit Fixed Point DSP, 24-Bit ALU and Accumulator Single-Cycle Multiply and ALU Operations Six-Level Hardware Stack Six Data RAM Pointers and Sixteen Program Memory Pointers RISC Processor with 30 Instruction Types * * * * GENERAL DESCRIPTION The Z893x3 products are high-performance Digital Signal Processors (DSP) with a modified Harvard architecture featuring separate program and dual data memory banks. The design is optimized for processing power with a minimum of silicon area. The Z893x3 16/24-Bit architecture accommodates advanced signal processing algorithms. The operating performance and efficient architecture provide deterministic instruction execution. Compression, filtering, frequency detection, audio, voice detection, speech synthesis, and other vital algorithms can all be implemented. DS000202-DSP0599 Six data RAM pointers provide circular buffer capabilities and simultaneous dual operand fetching. Three vectored interrupts are complemented by a six-level stack. By integrating a high-speed 4-channel, 8-bit A/D, SPI, three Counter/Timers with PWM and WDT support, and up to 40 bits of I/O, the Z893x3 family provides a compact low-cost system solution. To support a wide variety of development requirements, the Z893x3 DSP product family features the cost-effective Z89223/323 with 8 KWords of ROM. The Z89273/373, an 1 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG GENERAL DESCRIPTION (Continued) OTP version of the Z89223/323, is ideal for prototypes and early production builds. Throughout this specification, references to the Z893x3 device apply equally to the Z89223/273/323/373, unless otherwise specified. Notes: All signals with an overline are active Low. For example, in RD/WR, RD is active High and WR is active Low. For I/O ports, P1.3 denotes Port1 bit 3. Pins called NC are "No Connection"--they do not connect any power, grounds, or signals. Power connections follow conventional descriptions: Connection Power Ground Circuit VCC GND Device VDD VSS Program ROM/OTP 8192x16 PADDR DDATA0 Data RAM0 256x16 D0:0-3:0 DADDR0 DDATA1 Data RAM1 256x16 D0:1-3:1 DADDR1 Port 0 EA2-EA0 ED15-ED0 DS WAIT RD/WR PDATA 8 8 16 16 16-Bit Peripheral Interface 16 Program Control Unit HALT RESET CLKI CLKO Bank Switch 16 Phase Locked Loop X Y Addr Gen Unit0 P0:0 P1:0 P2:0 8 16 DDATA Addr Gen Unit1 P0:1 P1:1 P2:1 8 16 8-Bit A/D 16 16 16 MSB 16 VAHI AN0 AN1 AN2 AN3 VALO P1.0 or INT2 P1.1 or CLKOUT P1.2 or SDI P1.3 or SDO P1.4 or SS P1.5 or SCLK P1.6 or UI0 P1.7 or UI1 Stack Port 1 LPF Multiplier P 16 MSB 8-Bit I/O 24 VDD VSS AVCC AGND 24 ALU 24 Shifter 24 16 MUX 24 16-Bit Counter Timer, PWM 16-Bit Counter Timer, PWM SPI 16-Bit Counter Timer Port 2 P2.0 or INT0 P2.1 or INT1 P2.2 or TMO0 P2.3 or TMO1 P2.4 or WAIT P2.5 or UI2 P2.6 or TMO2 P2.7 8-Bit I/O Accumulator 24 16 MSB 4 Inputs 4 Outputs P3.7-P3.4 P3.3-P3.0 Figure 1. Z892X3/3x3 Functional Block Diagram 2 DS000202-DSP0599 ZiLOG External Bus and External Registers. The following is made to clarify naming conventions used in this specification. The external bus and external registers are external to Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter the DSP core, and are used to access internal and external peripherals. Z893x3 DSP Core OExternal BusO External Register External Register External Register External Register Internal Peripheral Internal Peripheral External Peripheral External Peripheral Figure 2. "External" Bus DS000202-DSP0599 3 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG PIN FUNCTIONS EA2-EA0. External Address Bus (output, latched). These VAHI. Analog High Reference Voltage (input). This pin pins provide the External Register Address. This address bus is driven during both internal and external accesses. One of up to seven user-defined external registers is selected by the processor for reads or writes. EXT7 is always reserved for use by the processor. ED15-ED0. External Data Bus (input/output). These pins are the data bus for the user-defined external registers, and are shared by Port0. These pins are normally tristated, except when these registers are specified as destination registers in a write instruction to an external peripheral, or when Port0 is enabled for output. This bus uses the control signals RD/WR, DS, and WAIT, and address pins EA2-EA0. DS. Data Strobe (output). This pin provides the data strobe provides the reference for the full scale voltage of the analog input signals. VALO. Analog Low Reference Voltage (input). This pin provides the reference for the zero voltage of the analog input signals. AVCC-AGND. Filtered Analog Power and Ground must be provided on separate pins to reduce digital noise in the analog circuits. Multifunction Pins. The Z89223/273/323/373 DSP fami- signal for the ED Bus. DS is active for transfers to/from external peripherals only. RD/WR. Read/Write Select (output). This pin controls the ly offers a user-configurable I/O structure, which means that most of the I/O pins offer dual functions. The function, direction (input or output), and for output, the characteristics (push-pull or open drain) are all under user-control, by programming the configuration registers appropriately as described in the I/O Ports section. The following share I/O Port pins: INT0-INT2. External Interrupts (input, edge-triggered). data direction signal for the External Data Bus. Data is available from the processor on ED15-ED0 when this signal and DS are both Low. WAIT. Wait State (input). This pin is sampled at the rising edge of the clock with appropriate setup and hold times. A single wait-state can be generated internally by setting the appropriate bits in the wait state register. The user must drive this line if multiple wait states are required. This pin is shared with Port2. CLKI. Clock (input). This pin is the clock circuit input. It These pins provide three of the eight interrupt sources to the Interrupt Controller. Each is programmable to be risingedge or falling-edge triggered. The other five interrupt sources are from the on-chip peripherals. CLKOUT. System Clock (output). This pin provides access to the internal processor clock. SDI. Serial Data In (input). This pin is the SPI serial data input. SDO. Serial Data Out (output). This pin is the SPI serial data can be driven by a signal or connected to a 32 KHz crystal. CLKO. Clock (output). This pin is the clock circuit output. output. SS. Slave Select (input). This pin is used in SPI Slave Mode only. SS advises the SPI that it is the target of a serial transfer from an external Master. SCLK. SPI Clock (output/input). This pin is an output in It is used for operation with a 32 KHz crystal and the PLL to generate the system clock. HALT. Halt State (input). This pin stops program execution. The processor continuously executes NOPs and the program counter remains constant while this pin is held Low. This pin offers an internal pull-up. RESET. Reset (input). This pin resets the processor. It push- Master mode and an input in Slave mode. UI0, UI1. User inputs (input). These general-purpose input es the contents of the Program Counter (PC) onto the stack and then fetches a new PC value from program memory address 0FFCH after the RESET signal is released. The Status register is set to all zeros. At power-up RAM and other registers are undefined, however, they are left unchanged with subsequent resets. RESET can be asserted asynchronously. AN0-AN3. Analog Inputs (input). These are the analog input pins. The analog input signal should be between VALO and VAHI for accurate conversions. pins are directly tested by the conditional branch instructions. They can also be read as bits in the status register. These are asynchronous input signals that require no special clock synchronization. Counter/Timer0 and Counter/Timer1 may use either of these pins as input. UI2. User Input (input). This pin is the input to Counter/Timer 2. TMO0/UO0. Counter/Timer Output or User Output 0 (output). Counter/Timer 0 and Counter/Timer 1 can be programmed to provide output on this pin. When User Outputs are enabled, and the Counter/Timer is disabled, this pin pro4 vides the complement of Status Register bit 5. DS000202-DSP0599 ZiLOG TMO1/UO1. Counter/Timer Output or User Output 1 (out- Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter put). Counter/Timer 0 and Counter/Timer 1 can be programmed to provide output on this pin. When User Outputs are enabled, and the Counter/Timer is disabled, this pin provides the complement of Status Register bit 6. TMO2. Counter/Timer 2 Output (output). This pin is the output of Counter/Timer 2 P0.15-P0.0. Port0 (input/output). This is a 16-bit user I/O Note: These pins are not bonded out on the 44-pin packages. P2.7-P2.0. Port2 (input/output). These pins are Port2 inputs or outputs when not configured as peripheral interfaces. The following seven pin functions preempt use of P2.6-P2.0 when enabled. INT0, INT1, TMO0/UO0, TMO1/UO1, WAIT, UI2, TMO2. P2.7 does not include a dual function. Note: P2.7-P2.5 are not bonded out on the 44-pin packages. port. Bits can be configured as input or output or globally as open-drain output. When enabled, Port0 uses the 16 data lines of the ED bus. The function of these pins can be dynamically changed by writing to the Port0 configuration registers. The High byte can also be configured to Port1 as described in the I/O Port section. P1.7-P1.0. Port1 (input/output). These pins are Port1 in- The following port pins are available only on the 80-pin package: P3.7-P3.4. Port3 (output). These pins are Port3 outputs. P3.3-P3.0. Port3 (input). These pins are Port3 inputs. puts or outputs when not configured for use as special purpose peripheral interface. The following eight pin functions preempt use of these pins when enabled. INT2, CLKOUT, SDI, SDO, SS, SCLK, UI0, UI1. DS000202-DSP0599 5 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG PIN CONFIGURATIONS ED15/P0.15 VSS ED14/P0.14 ED13/P0.13 ED12/P0.12 P2.0/INT0 VSS ED2/P0.2 ED1/P0.1 ED0/P0.0 VDD 6 ED3/P0.3 ED4/P0.4 VSS ED5/P0.5 ED6/P0.6 ED7/P0.7 ED8/P0.8 ED9/P0.9 VSS ED10/P0.10 ED11/P0.11 7 8 9 10 11 12 13 14 15 16 17 18 20 4 1 42 44-Pin PLCC 22 24 26 40 39 38 37 36 35 34 33 32 31 30 29 28 RESET LPF P2.2/TMO0/UO0 CLKO CLKI P2.4/WAIT DS P2.3/TMO1/UO1 EA2 EA1 EA0 Figure 3. 44-Pin PLCC Z89223/273 Pin Configuration 6 VAHI VALO AGND AN0 AN1 AN2 AN3 P2.1/INT1 AVCC VDD RD/WR DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter Table 1. 44-Pin PLCC Z89223/273 Pin Description No Symbol 1 2 3 4 5 6 7 8 9 P2.0/INT0 ED12/P0.12 ED13/P0.13 ED14/P0.14 VSS ED15/P0.15 ED3/P0.3 ED4/P0.4 VSS Function Port 2.0/Interrupt 0 External Data Bus/Port0 External Data Bus/Port0 External Data Bus/Port0 Ground External Data Bus/Port0 External Data Bus/Port0 External Data Bus/Port0 Ground External Data Bus/Port0 External Data Bus/Port0 External Data Bus/Port0 External Data Bus/Port0 External Data Bus/Port0 Ground External Data Bus/Port0 External Data Bus/Port0 Analog High Ref. Voltage Analog Low Ref. Voltage Analog Ground A/D Input 0 A/D Input 1 Direction Input/Output Input/Output Input/Output Input/Output No Symbol 23 AN2 24 AN3 25 P2.1/INT1 26 AVCC 27 VDD 28 RD/WR 29 EA0 30 EA1 31 EA2 32 P2.3/TMO1 33 DS 34 P2.4/WAIT 35 CLKI 36 CLKO 37 P2.2/TMO0 38 LPF 39 RESET 40 VDD 41 ED0/P0.0 42 ED1/P0.1 43 ED2/P0.2 44 VSS Function A/D Input 2 A/D Input 3 Port 2.1/Interrupt 1 Analog Power Power Supply R/W External Bus Ext Address 0 Ext Address 1 Ext Address 2 Port 2.3/Timer Output 1 Ext Data Strobe Port 2.4/Wait for ED Clock/Crystal In Clock/Crystal Out Port 2.2/Timer Output 0 PLL Low Pass Filter Reset Power External Data Bus/Port0 External Data Bus/Port0 External Data Bus/Port0 Ground Direction Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input Output Output Output Output Input/Output Output Input/Output Input Output Input/Output Input Input Input/Output Input/Output Input/Output 10 ED5/P0.5 11 ED6/P0.6 12 ED7/P0.7 13 ED8/P0.8 14 ED9/P0.9 15 VSS 16 ED10/P0.10 17 ED11/P0.11 18 VAHI 19 VALO 20 AGND 21 AN0 22 AN1 DS000202-DSP0599 7 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG PIN CONFIGURATIONS (Continued) ED15/P0.15 VSS ED14/P/P0.14 ED13/P0.13 ED12/P0.12 P2.0/INT0 VSS ED2/P0.2 ED1/P0.1 ED0/P0.0 VDD ED3/P0.3 ED4/P0.4 VSS ED5/P0.5 ED6/P0.6 ED7/P0.7 ED8/P0.8 ED9/P0.9 VSS ED10/P0.10 ED11/P0.11 1 3 5 7 9 11 44 43 42 41 40 39 38 37 36 35 34 33 31 44-Pin PQFP 29 27 25 23 12 13 14 15 16 17 18 19 20 21 22 VAHI VALO AGND AN0 AN1 AN2 AN3 P2.1/INT1 AVCC VDD RD/WR RESET LPF P2.2/TMO0/UO0 CLKO CLKI P2.4/WAIT DS P2.3/TMO1/UO1 EA2 EA1 EA0 Figure 4. 44-Pin PQFP Z89223/273 Pin Configuration 8 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter Table 2. 44-Pin PQFP Z89223/273 Pin Description No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Symbol ED3/P0.3 ED4/P0.4 VSS ED5/P0.5 ED6/P0.6 ED7/P0.7 ED8/P0.8 ED9/P0.9 VSS ED10/P0.10 ED11/P0.11 VAHI VALO AGND AN0 AN1 AN2 AN3 P2.1/INT1 AVCC VDD RD/WR Function External Data Bus/Port0 External Data Bus/Port0 Ground External Data Bus/Port0 External Data Bus/Port0 External Data Bus/Port0 External Data Bus/Port0 External Data Bus/Port0 Ground External Data Bus/Port0 External Data Bus/Port0 Analog High Ref. Voltage Analog Low Ref. Voltage Analog Ground A/D Input 0 A/D Input 1 A/D Input 2 A/D Input 3 Port 2.1/Interrupt 1 Analog Power Power R/W Exteral Output Bus Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input Input Input Input/Output No 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Symbol EA0 EA1 EA2 P2.3/TMO1 DS P2.4/WAIT CLKI CLKO P2.2/TMO0 LPF RESET VDD ED0/P0.0 ED1/P0.1 ED2/P0.2 VSS P2.0/INT0 ED12/P0.12 ED13/P0.13 ED14/P0.14 VSS ED15/P0.15 Function Ext Address 0 Ext Address 1 Ext Address 2 Port 2.3/Timer Output 1 Ext Data Strobe Port 2.4/Wait for ED Clock/Crystal In Clock/Crystal Out Port 2.2/Timer Output 0 PLL Low Pass Filter Reset Power Supply External Data Bus/Port0 External Data Bus/Port0 External Data Bus/Port0 Ground Port 2.0/Interrupt 0 External Data Bus/Port0 External Data Bus/Port0 External Data Bus/Port0 Ground External Data Bus/Port0 Direction Output Output Output Input/Output Output Input/Output Input Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output DS000202-DSP0599 9 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG PIN CONFIGURATIONS (Continued) RESET LPF P2.5/UI2 P2.2/TMO0/UO0 P2.6/TMO2 CLKO CLKI P2.4/ WAIT DS P2.3/TMO1/UO1 VDD EA2 EA1 EA0 HALT 45 40 35 33 32 30 48 VDD VSS ED0/P0.0 ED1/P0.1 ED2/P0.2 P1.0/INT2 VSS P1.1/CLKOUT P1.2/SDI P2.0/INT0 ED12/P0.12 ED13/P0.13 VDD ED14/P0.14 VSS ED15/P0.15 49 VSS 55 64-Pin TQFP 60 25 20 64 1 5 10 17 16 RD/WR VDD AVCC P2.1/INT1 VSS AN3 AN2 AN1 AN0 AGND P1.7/UI1 VALO P1.6/UI0 VSS VAHI ED11/P0.11 Figure 5. 64-Pin TQFP Z89323/373 Pin Configuration 10 ED3/P0.3 ED4/P0.4 VSS VDD ED5/P0.5 P1.3/SDO ED6/P0.6 P1.4/SS ED7/P0.7 P1.5/SCLK P2.7 ED8/P0.8 ED9/P0.9 VSS ED10/P0.10 VSS DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter Table 3. 64-Pin TQFP Z89223/273 Pin Description No Symbol 1 2 3 4 5 6 7 8 9 ED3/P0.3 ED4/P0.4 VSS VDD ED5/P0.5 P1.3/SDO ED6/P0.6 P1.4/SS ED7/P0.7 Function External Data Bus/Port0 External Data Bus/Port0 Ground Power Supply External Data Bus/Port0 Port 1.3/Serial Output External Data Bus/Port0 Port 1.4/Slave Select External Data Bus/Port0 Port 1.5/Serial Clock Port 2.7 External Data Bus/Port0 External Data Bus/Port0 Ground External Data Bus/Port0 Ground External Data Bus/Port0 Analog High Ref. Voltage Ground Port 1.6/User Input 0 Analog Low Ref. Voltage Port 1.7/User Input 1 Analog Ground A/D Input 0 A/D Input 1 A/D Input 2 A/D Input 3 Ground Port 2.1/Interrupt 1 Analog Power Power Supply R/W External Bus Direction Input/Output Input/Output No Symbol 33 HALT 34 EA0 35 EA1 36 EA2 Function Halt Execution Ext Address 0 Ext Address 1 Ext Address 2 Power Supply Port2.3/Timer Output 1 Ext Data Strobe Port 2.4/Wait for ED Clock/Crystal In Clock/Crystal Out Port 2.6/Timer Output 2 Port 2.2/Timer Output 0 Port 2.5/User Input 2 PLL Low Pass Filter Reset Ground Power Supply Ground External Data Bus/Port0 External Data Bus/Port0 External Data Bus/Port0 Port 1.0/Interrupt 2 Ground Direction Input Output Output Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input 37 VDD 38 P2.3/TMO1 39 DS 40 P2.4/WAIT 41 CLKI 42 CLKO 43 P2.6/TMO2 44 P2.2/TMO0 45 P2.5/UI2 46 LPF 47 RESET 48 VSS 49 VDD 50 VSS 51 ED0/P0.0 52 ED1/P0.1 53 ED2/P0.2 54 P1.0/INT2 55 VSS Input/Output Output Input/Output Input Output Input/Output Input/Output Input/Output Input Input 10 P1.5/SCLK 11 P2.7 12 ED8/P0.8 13 ED9/P0.9 14 VSS 15 ED10/P0.10 16 VSS 17 ED11/P0.11 18 VAHI 19 VSS 20 P1.6/UI0 21 VALO 22 P1.7/UI1 23 AGND 24 AN0 25 AN1 26 AN2 27 AN3 28 VSS 29 P2.1/INT1 30 AVCC 31 VDD 32 RD/WR Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input Input Input Input Input/Output 56 P1.1/CLKOUT Port 1.1/Clock Output 57 P1.2/SDI 58 P2.0/INT0 59 ED12/P0.12 60 ED13/P0.13 61 VDD 62 ED14/P0.14 63 VSS Port 1.2/Serial Input Port 2.0/Interrupt 0 External Data Bus/Port0 External Data Bus/Port0 Power Supply External Data Bus/Port0 Ground External Data Bus/Port0 Input/Output Input/Output Output 64 ED15/P0.15 DS000202-DSP0599 11 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG PIN CONFIGURATIONS (Continued) NC ED15/P0.15 VSS ED14/P0.14 VDD ED13/P0.13 ED12/P0.12 P2.0/INT0 P1.2/SDI P1.1/CLKOUT VSS P1.0/INT2 ED2/P0.2 ED1/P0.1 ED0/P0.0 VSS VDD 9 NC ED3/P0.3 ED4/P0.4 VSS VDD ED5/P0.5 P1.3/SDO ED6/P0.6 P1.4/SS ED7/P0.7 P1.5/SCLK P2.7 ED8/P0.8 ED9/P0.9 VSS ED10/P0.10 VSS 10 1 61 60 VSS RESET LPF P2.5/UI2 P2.2/TMO0/UO0 P2.6/TMO2 CLKO CLKI P2.4/WAIT DS P2.3/TMO1/UO1 VDD NC EA2 EA1 EA0 HALT 68-Pin PLCC 26 27 44 43 Figure 6. 68-Pin PLCC Z89323/373 Pin Configuration 12 ED11/P0.11 VDD VAHI VSS P1.6/UI0 VALO P1.7/UI1 AGND AN0 AN1 AN2 AN3 VSS P2.1/INT1 AVCC VDD RD/WR DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter Table 4. 68-Pin PLCC Z89323/373 Pin Description No Symbol 1 2 3 4 5 6 7 8 9 P1.2/SDI P2.0/INT0 ED12/P0.12 ED13/P0.13 VDD ED14/P0.14 VSS ED15/P0.15 NC Function Port 1.2/Serial Input Port 2.0/Interrupt 0 External Data Bus/Port0 External Data Bus/Port0 Power Supply External Data Bus/Port0 Ground External Data Bus/Port0 No Connection No Connection External Data Bus/Port0 External Data Bus/Port0 Ground Power Supply External Data Bus/Port0 Port 1.3/Serial Output External Data Bus/Port0 Port 1.4/Slave Select External Data Bus/Port0 Port 1.5/Serial Clock Port 2.7 External Data Bus/Port0 External Data Bus/Port0 Ground External Data Bus/Port0 Ground External Data Bus/Port0 Power Supply Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output No Symbol 35 AN0 36 AN1 37 AN2 38 AN3 39 VSS 40 P2.1/INT1 41 AVCC 42 VDD 43 RD/WR 44 HALT Function A/D Input 0 A/D Input 1 A/D Input 2 A/D Input 3 Ground Port 2.1/Interrupt 1 Analog Power Power Supply R/W External Bus Halt Execution Ext Address 0 Ext Address 1 Ext Address 2 No Connection Power Supply Port2.3/Timer Output 1 Ext Data Strobe Port 2.4/Wait for ED Clock/Crystal In Clock/Crystal Out Port 2.6/Timer Output 2 Port 2.2/Timer Output 0 Port 2.5/User Input 2 PLL Low Pass Filter Reset Ground Power Supply Ground External Data Bus/Port0 External Data Bus/Port0 External Data Bus/Port0 Port 1.0/Interrupt 2 Ground Port 1.1/Clock Output Direction Input Input Input Input Input/Output Output Input Output Output Output 10 NC 11 ED3/P0.3 12 ED4/P0.4 13 VSS 14 VDD 15 ED5/P0.5 16 P1.3/SDO 17 ED6/P0.6 18 P1.4/SS 19 ED7/P0.7 20 P1.5/SCLK 21 P2.7 22 ED8/P0.8 23 ED9/P0.9 24 VSS 25 ED10/P0.10 26 VSS 27 ED11/P0.11 28 VDD 29 VAHI 30 VSS 31 P1.6/UI0 32 VALO 33 P1.7/UI1 34 AGND Input/Output Input/Output 45 EA0 46 EA1 47 EA2 48 NC Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output 49 VDD 50 P2.3/TMO1 51 DS 52 P2.4/WAIT 53 CLKI 54 CLKO 55 P2.6/TMO2 56 P2.2/TMO0 57 P2.5/UI2 58 LPF 59 RESET 60 VSS 61 VDD 62 VSS 63 ED0/P0.0 64 ED1/P0.1 65 ED2/P0.2 66 P1.0/INT2 67 VSS 68 P1.1/CLKOUT Input/Output Output Input/Output Input Output Input/Output Input/Output Input/Output Input Input Analog High Ref. Voltage Input Ground Port 1.6/User Input 0 Analog Low Ref. Voltage Port 1.7/User Input 1 Analog Ground Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output DS000202-DSP0599 13 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG PIN CONFIGURATIONS (Continued) RESET P3.7 LPF P2.5/UI2 P2.2/TMO0/UO0 P2.6/TMO2 CLKO CLKI P2.4/WAIT DS P2.3/TMO1/UO1 VDD 60 55 50 64 VSS P30 ED0/P0.0 ED1/P0.1 ED2/P0.2 P1.0/INT2 VSS P1.1/CLKOUT P1.2/SDI P2.0/INT0 ED12/P0.12 ED13/P0.13 VDD ED14/P0.14 VSS P3.1 80 1 65 NC EA2 EA1 P3.6 EA0 HALT NC P3.5 RD/WR 45 41 40 VDD AVCC P2.1/INT1 VSS NC VDD VSS 70 35 80-Pin PQFP 75 30 AN3 AN2 AN1 AN0 AGND P1.7/UI1 VALO P1.6/UI0 VSS VAHI VDD 25 5 VDD 10 15 20 P3.3 ED10/P0.10 VSS 24 NC P3.4 ED11/P0.11 NC ED15/P0.15 NC NC ED3/P0.3 P3.2 ED4/P0.4 VSS Figure 7. 80-Pin PQFP Z89323/373 Pin Configuration 14 ED5/P0.5 P1.3/SDO ED6/P0.6 P14/SS ED7/P0.7 P1.5/SCLK P2.7 ED8/P0.8 ED9/P0.9 VSS DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter Table 5. 80-Pin PQFP Z89323/373 Pin Description No Symbol 1 2 3 4 5 6 7 8 9 NC ED15/P0.15 NC NC ED3/P0.3 P3.2 ED4/P0.4 VSS VDD Function No Connection External Data Bus/Port0 No Connection No Connection External Data Bus/Port0 Port 3.2 External Data Bus/Port0 Ground Power Supply External Data Bus/Port0 Port 1.3/Serial Output External Data Bus/Port0 Port 1.4/Slave Select External Data Bus/Port0 Port 1.5/Serial Clock Port 2 7 External Data Bus/Port0 External Data Bus/Port0 Ground Port 3 3 External Data Bus/Port0 Ground No Connection Port 3.4 External Data Bus/Port0 Power Supply Direction Input/Output No Symbol 41 RD/WR 42 P3.5 43 NC 44 HALT Function R/W External Bus Port 3.5 No Connection Halt Execution Ext Address 0 Port 3.6 Ext Address 1 Ext Address 2 No Connection Power Supply Port 2.3/Timer Output 1 Ext Data Strobe Port 2.4/Wait for ED Clock/Crystal In Clock/Crystal Out Port 2.6/Timer Output 2 Port 2.2/Timer Output 0 Port 2.5/User Input 2 PLL Low Pass Filter Port 3.7 Reset Ground Power Supply No Connection Ground Port 3.0 External Data Bus/Port0 External Data Bus/Port0 External Data Bus/Port0 Port 1.0/Interrupt 2 Ground Port 1.1/Clock Output Port 1.2/Serial Input Port 2.0/Interrupt 0 External Data Bus/Port0 External Data Bus/Port0 Power Supply External Data Bus/Port0 Ground Port 3.1 Direction Output Output Input Output Output Output Output Input/Output Input Input/Output 45 EA0 46 P3.6 47 EA1 48 EA2 49 NC 10 ED5/P0.5 11 P1.3/SDO 12 ED6/P0.6 13 P1.4/SS 14 ED7/P0.7 15 P1.5/SCLK 16 P2.7 17 ED8/P0.8 18 ED9/P0.9 19 VSS 20 P3.3 21 ED10/P0.10 22 VSS 23 NC 24 P3.4 25 ED11/P0.11 26 VDD 27 VAHI 28 VSS 29 P1.6/UI0 30 VALO 31 P1.7/UI1 32 AGND 33 AN0 34 AN1 35 AN2 36 AN3 37 VSS 38 P2.1/INT1 39 AVCC 40 VDD Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output 50 VDD 51 P2.3/TMO1 52 DS 53 P2.4/WAIT 54 CLKI 55 CLKO 56 P2.6/TMO2 57 P2.2/TMO0 58 P2.5/UI2 59 LPF 60 P3.7 61 RESET 62 VSS 63 VDD Input/Output Output Input/Output Input Output Input/Output Input/Output Input/Output Input Output Input Output Input/Output 64 NC 65 VSS 66 P3.0 67 ED0/P0.0 68 ED1/P0.1 69 ED2/P0.2 70 P1.0/INT2 71 VSS 72 P1.1/CLKOUT 73 P1.2/SDI 74 P2.0/INT0 75 ED12/P0.12 76 ED13/P0.13 77 VDD 78 ED14/P0.14 79 VSS 80 P3.1 Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Analog High Ref. Voltage Input Ground Port 1 6/User Input 0 Analog Low Ref. Voltage Port 1 7/User Input 1 Analog Ground A/D Input 0 A/D Input 1 A/D Input 2 A/D Input 3 Ground Port 2.1/Interrupt 1 Analog Power Power Supply Input/Output Input Input Input Input Input/Output Input Input/Output DS000202-DSP0599 15 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG ABSOLUTE MAXIMUM RATINGS Symbol VCC TSTG TA Description Supply Voltage Ambient Operating Temperature "S" device "E" device Min -0.3 Max 7.0 150 Units V C Storage Temperature -65 0 -40 70 85 C C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This rating is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended period may affect device reliability. STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin. Positive current I(+) flows in to the referenced pin. Negative current I() flows out of the referenced pin. I (+) I (-) From Output Under Test 2.1 K 30 pF 9.1 K Figure 8. Test Load Diagram 16 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter DC ELECTRICAL CHARACTERISTICS Table 6. ROM Version: VDD = 5V 10%, TA = 0C to +70C for "S" temperature range TA = -40C to +85C for "E" temperature range, unless otherwise noted; IDD measured with peripherals disabled Symbol Parameter IDD-PLL Supply Current using PLL IDD-ECD Supply Current using External Clock Direct IDD-XOD Supply Current using XTAL Oscillator Direct IDD-DEEP Supply Current during Deep Sleep VIH VIL IL VOH VOL IFL Input High Level Input Low Level Input Leakage Output High Voltage Output Low Voltage Output Floating Leakage Current IOH = -100 A IOH = -160 A IOL = 1.6 mA IOL = 2.0 mA -10A -10A VDD-0.2V 2.4V 0.4V 0.5V 10A Condition VDD = 5.0V, 20 MHz VDD = 5.0V, 20 MHz VDD = 5.0V, 32-kHz XTAL VDD = 5.0V, 32kHz XTAL 2.7V 0.8V 10A Min Typical 60mA 55 mA 250A 175A Max 66mA 61mA 275A 193A Table 7. OTP Version: VDD = 5V 10%, TA = 0C to +70C for "S" temperature range TA = -40C to +85C for "E" temperature range, unless otherwise noted; IDD measured with peripherals disabled Symbol Parameter IDD-PLL IDD-ECD Supply Current using PLL Supply Current using External Clock Direct Condition VDD = 5.0V, 20 MHz VDD = 5.0V, 20 MHz VDD = 5.0V, 32-kHz XTAL VDD = 5.0V, 32kHz XTAL 2.7V 0.8V -10A IOH = -100 A IOH = -160 A VOL IFL Output Low Voltage Output Floating Leakage Current IOL = 1.6 mA IOL = 2.0 mA -10A VDD-0.2V 2.4V 0.4V 0.5V 10A 10A Min Typical 78mA 75mA 17mA 17mA Max 86mA 83mA 19mA 19mA IDD-XOD Supply Current using XTAL Oscillator Direct IDD-DEEP Supply Current during Deep Sleep VIH VIL IL VOH Input High Level Input Low Level Input Leakage Output High Voltage DS000202-DSP0599 17 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG DC ELECTRICAL CHARACTERISTICS (Continued) 60 50 40 30 20 10 0 0 5 10 15 20 25 System Clock [MHz] Direct Clock with VCO Off PLL Clock from 32.8KHz Crystal I DD [mA] Figure 9. Z89373 Typical OTP Current Consumption 18 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter AC ELECTRICAL CHARACTERISTICS Table 8. VDD= 5V 10%, TA = 0C to +70C for "S" Temperature Range TA = -40C to +85C for "E" temperature range, unless otherwise noted Symbol Clock TCY CPWH CPWL Tr Tf Parameter CLKI Cycle Time for user-supplied clock CLKI Pulse Width High CLKI Pulse Width Low CLKI Rise Time for 20-MHz user-supplied clock CLKI Fall Time for 20-MHz user-supplied clock Min [ns] 50 21 21 Max [ns] 31250 2 2 10 4 10 0 15 0 5 2 20 TCY 2 TCY 1TCY 3 TCY 7 TBD 10 15 1/2 SCLK Period 15 10 External Peripheral Bus EASET EA Setup Time to DS Fall EAHOLD EA Hold Time from DS Rise RWSET Read/Write Setup Time to DS Fall RWHOLD Read/Write Hold Time from DS Rise RDSET Data Read Setup Time to DS Rise RDHOLD Data Read Hold Time from DS Rise WRVALID Data Write Valid Time from DS Fall WRHOLD Data Write Hold Time from DS Rise Reset RRISE Reset Rise Time RWIDTH Reset Low Pulse Width Interrupt IWIDTH Interrupt Pulse Width Halt HWIDTH Halt Low Pulse Width Wait State WLAT Wait Latency Time from DS Fall WDEA Wait Deassert Setup Time to CLKOUT Rise SPI SDI-SCLK Serial Data In to Serial Clock Setup Time SCLK-SDO Serial Clock to Serial Data Out Valid SS-SCLK Slave Select to Serial Clock Setup Time SS-SDO Slave Select to Serial Data Out Valid SCLK-SDI Serial Clock to Serial Data In Hold Time DS000202-DSP0599 19 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG 8-BIT ANALOG/DIGITAL CONVERTER Table 9. AVCC-AGND = 5V 10% TA = 0C to +70C for "S" temperature range, unless otherwise noted Parameter Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Zero Offset Error Full Scale Offset Error Valid Input Signal Range Input Capacitance Conversion Time Input Impedance 500kSPS 100kSPS 44kSPS VAHI VALO VAHI-VALO Reference Ladder Resistance VAHI to VALO Power Dissipation Min Typ 0.5 0.5 2 2 VALO 2 33 3 10 48 110 VALO + 2.5 AGND 2.5 5 50 85 AVCC AVCC2.5 AVCC Max 1 1 3 3 VAHI 40 Units LSB LSB LSB LSB V pF s k k k V V V k mW Table 10. AVCC-AGND = 5V 10% TA = -40C to +85C for "E" temperature range, unless otherwise noted Parameter Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Zero Offset Error Full Scale Offset Error Valid Input Signal Range Input Capacitance Conversion Time Input Impedance 500kSPS 100kSPS 44kSPS VAHI VALO VAHI-VALO Reference Ladder Resistance VAHI to VALO Power Dissipation Min Typ Max 1 1 4 4 VAHI 40 Units LSB LSB LSB LSB V pF s k k k V V V k 85 mW 3 3 VALO 2 33 3 10 48 110 VALO + 2.5 AGND 2.5 5 AVCC AVCC2.5 AVCC 20 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter TIMING DIAGRAMS TCY CPWL Tr CPWH Tf Figure 10. Clock Timing RD/WR RWSET DS RWHOLD EASET EA(2:0) Valid Address Out EAHOLD RDSET RDHOLD ED(15:0) Data Figure 11. Read Timing RD/WR DS WLAT WAIT WDEA CLKOUT EA(2:0) Valid Address Out RDSET RDHOLD ED(15:0) Data Figure 12. Read Timing Using WAIT Pin DS000202-DSP0599 21 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG TIMING DIAGRAMS (Continued) RD/WR RWSET DS RWHOLD EASET EA(2:0) Valid Address Out WRVALID EAHOLD WRHOLD ED(15:0) Data Figure 13. Write Timing RD/WR RWSET DS WLAT WAIT WDEA CLKOUT EASET EA(2:0) Valid Address Out RWHOLD WRVALID ED(15:0) Data WRHOLD Figure 14. Write Timing Using WAIT Pin 22 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter SS* SS-SDO Valid SCLK* SCLK-SDO Valid SDO TRI-STATE SS-SCLK Setup Valid SDI-SCLK Setup SDI Valid SCLK-SDI Hold *Notes: The polarity of SCLK and SS are programmable by the user. SS is used in Slave Mode only. This figure illustrates data transmission on the falling edge of SCLK, data reception on the rising edge of SCLK, with SS active Low (default). Figure 15. SPI Timing (Master and Slave Modes) DS000202-DSP0599 23 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG FUNCTIONAL DESCRIPTION Instruction Timing. Most instructions are executed in one machine cycle. A multiplication or multiply/accumulate instruction requires a single cycle. Long immediate instructions, and Jump or Call instructions, are executed in two machine cycles. Specific instruction cycle times are described in the Instruction Description section. Multiply/Accumulate. The multiplier can perform a 16Data Bus Bank Switch. There is a switch that connects the X Bus to the DDATA Bus that allows both the X and Y registers to be loaded with the same operand for a one cycle squaring operation. The switch is also used to read the X register. ALU. The ALU features two input ports. One is connected bit x 16-bit multiply, or multiply/accumulate, in one machine cycle using the Accumulator and/or both the X and Y inputs. The multiplier produces a 32-bit result, however, only the 24 most significant bits are saved for the next instruction or accumulation. For operations on very small numbers where the least significant bits are important, the data should first be scaled to avoid truncation errors. to the output of the 24-bit Accumulator. The other input selects either the Multiplier Unit Output or the 16-bit DDATA bus (left-justified with zeros in the eight LSBs). The ALU performs arithmetic, logic, and shift operations. DDATA Multiplier Unit Output 16 XDATA 16 16 DDATA 24 MUX *X Register (16) Y Register (16) 24 24 MULTIPLIER P Register (24) 16 MSB ALU 24 Shift Unit 24 *Options: No Shift 3 Bits Right Accumulator (24) 16 MSB Multiplier Unit Output Figure 17. ALU Block Diagram Hardware Stack. A six-level hardware stack is connected Figure 16. Multiplier Block Diagram All inputs to the multiplier should be fractional two's-complement, 16-bit binary numbers, which places them in the range [-1 to 0.9999695]. The result is in 24 bits, so the range is [-1 to 0.9999999]. If 8000H is loaded into both the X and Y registers, the multiplication produces an incorrect result. Positive one cannot be represented in fractional notation, and the multiplier actually yields the result 8000H x 8000H = 8000H (-1 x -1 = -1). The user should avoid this case to prevent erroneous results. A shifter between the P Register and the Multiplier Unit Output can shift the data by three bits right or no shift. 24 to the DDATA bus to hold subroutine return addresses or data. The CALL instruction pushes PC+2 onto the stack, and the RET instruction pops the contents of the stack to the PC. User Inputs and Outputs. The Z893x3 features three User Inputs, UI0, UI1, and UI2. Pins UI0 and UI1 are connected directly to status register bits S10 and S11, and can be read, or used as a condition code in any conditional instruction. Pins UI0, UI1 and UI2 may also be used to clock the Counter/Timers. There are two user output bits, UO0 and UO1, which share pins with the timer outputs TMO0 and TMO1 on Port2. When the User Outputs are enabled, they are the complements of bits S5 and S6 of the Status Register. DS000202-DSP0599 ZiLOG Interrupts. The Z893x3 features three user interrupt inputs Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter Port2. A multifunctional 8-bit port. Bits can be configured as input or output or globally as open-drain output. Port2 also supports INT0 and INT1, all three Counter/Timer outputs, ED Bus, WAIT, and UI2. Port3. Port3 is an 8-bit user I/O port with 4 bits of input and 4 bits of output. It is available only on the 80-pin package. External Register Usage. T h e e x t e r n a l r e g i s t e r s EXT0-EXT6 are accessed using the External Address Bus EA2-EA0, the External Data Bus (ED Bus) ED15-ED0, and control signals DS, WAIT, and RD/WR. These provide a convenient data transfer capability with external peripherals. Data transfers can be performed in a single-cycle. An internal wait state generator is provided to accommodate slower external peripherals. A single wait state can be implemented through control register Bank15/EXT3. For additional wait states, the WAIT pin can be used. The WAIT pin is monitored only during execution of a read or write instruction to external peripherals on the ED bus. Wait-State Generator. An internal Wait-State generator which can be programmed to be positive or negative edgetriggered. There are five interrupts generated by internal peripherals: the A/D converter, the Serial Peripheral Interface, and the three Counter/Timers. Internally there are three priority levels. The internal signals for Interrupt service Requests are denoted ISR0, ISR1, and ISR2, with ISR0 having the highest priority, and ISR2 the lowest. The user can program which interrupt sources are enabled, and which sources are serviced by the highest, middle, and lowest priority service routines. An interrupt is serviced at the end of an instruction execution. Two machine cycles are required to enter an interrupt instruction sequence. The PC is pushed onto the stack. The Interrupt Controller fetches the address of the interrupt service routine from the following locations in program memory: Device Z89223/273/323/373 ISR0 1FFFH ISR1 1FFEH ISR2 1FFDH At the end of the interrupt service routine, a RET instruction is used to pop the stack into the PC. The Set-Interrupt-Enable-Flag (SIEF) instruction enables the interrupts. Interrupts are automatically disabled when entering an interrupt service routine. Before exiting an interrupt service routine the SIEF instruction can be used to reenable interrupts. Registers. In addition to the internal registers for process- is provided to accommodate slow external peripherals. A single Wait-State can be implemented through a control register. For additional states, a dedicated pin (WAIT) can be held Low. The WAIT pin is monitored only during execution of a read or write instruction to external peripherals (ED bus). Analog to Digital Converter. The A/D Converter is a 4- ing, control, and configuration, the Z893x3 offers up to seven user-defined 16-bit external registers, EXT0-EXT6, depending on the Register Bank Select value. The external register address space is shared by the Z893x3 internal peripherals. Selecting banks 0-4 of the EXT Register Assignment allows access to/from three to seven of these addresses for general-purpose use. I/O Ports. The Z893X3 DSP family features a user-config- channel, 8-bit half-flash converter. Two external reference voltages provide a scalable input range. The A/D sample rate is determined by a prescaler connected to the system clock. An interrupt is optionally generated at the end of a conversion. The four input channels can be programmed to operate on demand, continuously, or upon an event (timer or interrupt). Counter/Timers (C/T0 and C/T1). These C/Ts are 16-bit urable I/O structure. Most of the I/O pins include dual functions. The Counter/Timer, Serial Peripheral Interface, and External Interrupt Enables determine whether a pin is dedicated to peripheral or I/O port use. Port0. A 16-bit user I/O port. Bits can be configured as input or output or globally as open-drain output. When enabled, Port0 consumes the 16 data lines used by the ED bus. Port0 function and ED bus use can be dynamically alternated by enabling and disabling Port0. Port1. A multifunctional 8-bit port. Bits can be configured as input or output or globally as open-drain output. Port1 also supports INT2, CLKOUT, the Serial Peripheral Interface, and User Inputs 0 and 1. with 8-bit prescalers. They also offer the option of being used as PWM generators and include both hardware and software Watch-Dog capabilities. Both C/Ts are identical and can be externally or internally clocked. Either C/T can drive TMO0 or TMO1. Either C/T can drive any of the three interrupt service requests (ISR0, ISR1, or ISR2). Counter/Timer (C/T2). This C/T is 16-bits, externally or internally clocked, and can drive TMO2 and/or any of the three interrupt service requests (ISR0, ISR1, or ISR2). Serial Peripheral Interface (SPI). The Serial Peripheral Interface provides a convenient means of inter-processor and processor-peripheral communication. It offers the capability to transmit and receive simultaneously. The SPI is designed to operate in either master or slave mode. DS000202-DSP0599 25 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG MEMORY MAP Program Memory. Programs of up to 8K words can be masked into internal ROM (Z89323) or programmed into OTP (Z89373). Four locations are dedicated to the vector addresses for the three interrupt service routines (1FFDH-1FFFH) and for the starting address following a RESET (1FFCH). Internal ROM is mapped from 0000H to 1FFFH, and the highest location for program instructions is 1FFBH. Internal Data RAM. All Z893x3 family members feature internal 512 x 16-bit data RAM organized as two banks of 256 x 16-bit words each (RAM0 and RAM1). The three addressing modes available to access the data RAM are direct addressing, short form direct, and register indirect. In auto-increment, loop-increment, and loop-decrement indirect addressing, the pointer is automatically modified. The data RAM pointers, which may be read or written directly, are 8-bit registers connected to the lower byte of the internal 16-bit DDATA Bus. Program Memory Pointers. The first 16 locations of each data RAM bank can be used as pointers to locations in Program Memory. These pointers provide an efficient way to address coefficients. The programmer selects a pointer location using two bits in the status register and two bits in the operand. At any one time, there are eight usable pointers, four per bank, and the four pointers are in consecutive locations. Example: Dn:b, where n = pointer number = 0, 1, 2, or 3 b = bank = 0 or 1, thus, D0:0, D1:0, D2:0, D3:0 for RAM0 D0:1, D1:1, D2:1, D3:1 for RAM1 If S3/S4 = 01 in the status register, then D0:0/D1:0/D2:0/D3:0 refer to register locations 4/5/6/7 in data RAM Bank 0. The contents of both data RAM banks can be read simultaneously and loaded into the X and Y inputs of the multiplier during a multiply instruction. The addresses for each data RAM bank are: 0255 (0000H00FFH) for RAM0 256511 (0100H01FFH) for RAM1 Data RAM Pointers. In register indirect, each data RAM bank is addressed by one of three data RAM address pointers: Example: Pn:b, where n = pointer number = 0, 1, or 2 b = bank = 0 or 1, thus, P0:0, P1:0, P2:0 for RAM0 P0:1, P1:1, P2:1 for RAM1 Data Memory FFFF Program Memory FFFF FFFC Not Used Not Used Or 512 words 01FF 8 KW 1FFF-D 1FFC 1FFB 0000 DRAM1 DRAM0 ISR0-ISR2 Vectors RESET Vector 0100 00FF 0000 On-Chip Memory On-Chip Memory Figure 18. Memory Map 26 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter REGISTERS Both external and internal registers are accessed in one machine cycle. The external registers are used to access the onchip peripherals when they are enabled. The internal registers of the Z893X3 are defined below: SR Bit Register X Y P A Pn:b PC SR EXT0 EXT1 EXT2 EXT3 EXT4 EXT5 EXT6 EXT7 Register Definition Multiplier X Input, 16-bits Multiplier Y Input, 16-bits Multiplier Output, 24-bits Accumulator, 24-bits Six Data RAM Pointers, 8-bits each Program Counter, 16-bits Status Register, 16-bits depends on Bank Select #, 16-bits depends on Bank Select #, 16-bits depends on Bank Select #, 16-bits depends on Bank Select #, 16-bits depends on Bank Select #, 16-bits depends on Bank Select #, 16-bits depends on Bank Select #, 16-bits Interrupt Status/Bank Select, 16-bits S15 (N) S14 (OV) S13 (Z) S12 (C) S11 (UI1) S10 (UI0) S9 (SH3) only be read by software. S9-S0 control hardware operations and can be written by software. Table 11. Status Register Bit Functions Function ALU Negative ALU Overflow ALU Zero Carry User Input 1 User Input 0 MPY Output Arithmetically Shifted Right by Three Bits Overflow Protection Interrupt Enable User Output 1 User Output 0 "Short Form Direct" bits RAM Pointer Loop Size Read/Write RO RO RO RO RO RO R/W S8 (OP) S7 (IE) S6 (UO1) S5 (UO0) S4-S3 S2-S0 (RPL) R/W R/W R/W R/W R/W R/W X and Y are two 16-bit input registers for the multiplier. These registers can be utilized as temporary registers when the multiplier is not being used. P holds the result of multiplications and is read-only. A is a 24-bit Accumulator. The output of the ALU is sent Note: RO = read only, RW = read/write. The status register can always be read in its entirety. S15-S12 are set/reset by the ALU after an operation. S11-S10 are set/reset by the user input pins. to this register. When 16-bit data is transferred into this register, it is placed into the 16 MSBs and the least significant eight bits are set to zero. Only the upper 16 bits are transferred to the destination register when the Accumulator is selected as a source register in transfer instructions. Pn:b are the pointer registers for accessing data RAM where If S9 is set and a multiply/shift option is used, the shifter shifts the result three bits right. This feature allows the data to be scaled and prevents overflows. If S8 is set, the hardware clamps at maximum positive or negative values instead of overflowing. S7 enables interrupts. S6-S5 are User Outputs. The complement of the value in n = 0, 1, or 2, and b = 0 or 1. They can be directly read or written. They point to locations in data RAM. PC is the Program Counter. Any instruction which may modify this register requires two clock cycles. SR is the status register. It contains the ALU status and pro- the Status Register appears on bits 2 and 3 of Port2 if the User Outputs are enabled by writing a 1 to Bit 15 of Bank 15-EXT3, and Counter/Timer 0 and 1 are disabled. S4-S3 are the two MSBs in the "short form direct" mode cessor control bits. The status register can always be read in its entirety. S15-S10 are set/reset by hardware and can of addressing. S2-S0 define the RAM pointer loop size as indicated in Ta- ble 12. DS000202-DSP0599 27 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG REGISTERS (Continued) Table 12. RPL Description S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Loop Size 256 2 4 8 16 32 64 128 Dn:b refers to locations in RAM that can be used as a pointer to locations in program memory which is efficient for coefficient addressing. The programmer decides which location to choose from two bits in the status register and two bits in the operand. Thus, only the lower 16 possible locations in RAM can be specified. At any one time, there are eight usable pointers, four per bank, and the four pointers are in consecutive locations in RAM. For example, if S3/S4=01 in the status register, then D0:0/D1:0/D2:0/D3:0 refer to register locations 4/5/6/7 in RAM Bank 0. Note that when the data pointers are being written to, a number is actually being loaded to Data RAM, so they can be used as a limited method for writing to RAM. EXTn are external registers (n = 0 to 6). These are seven 16-bit register addresses provided for mapping internal and external peripherals into the address space of the processor. Note that for external peripherals the actual register RAM does not exist on the chip, but would exist as part of the external device, such as an A/D result latch. The External Address Bus, EA2-EA0, the External Data Bus, ED15-ED0, DS, WAIT, and RD/WR are used to access external peripherals. EXT7 is used for Register Bank Select, and to program wait states for EXT0-EXT6, and is not available for accessing an external peripheral. The following are not actually registers, but are read or written in the same way as hardware registers on the chip: Register BUS Dn:b EXTn Register Definition D-Bus Eight Data Pointers External Register, 16-bit BUS is a read-only register which, when accessed, returns the contents of the D-Bus. BUS is used for emulation only. N S15 Negative Overflow Zero Carry User Input UI1,UI0 (Read Only) MPY output arithmetically shifted right by three bits Overflow Protection OV S14 Z S13 C S12 UI1 S11 UI0 SH3 S10 S9 OP S8 IE S7 UO1 UO0 S6 S5 S4 S3 S2 RPL S1 S0 Ram Pointer 000 001 010 011 100 101 110 111 Loop Size 256 2 4 8 16 32 64 128 "Short Form Direct" bits User Output UO1, UO0 (Complemented) Global Interrupt Enable Figure 19. Status Register 28 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter BANK/EXT REGISTER ASSIGNMENTS There are 16 different Banks of EXT registers. Control of the bank switching is done via the EXT7 register. The same EXT7 register exists in all Banks. Banks 0-5 support different combinations of external registers for external peripherals, and external registers for internal (on-chip) peripherals. Use the bank that offers the optimum combination of internal and external registers to support the application. Use it as a preferred working bank to minimize bank switching. Banks 6-12 only decode EXT6 and EXT7. Do not use EXT0-5 for Banks 6-12. Banks 13-15 are control register banks. These banks are used in the initialization routines and whenever a configuration change is required. Refer to the sections on I/O Ports and Peripherals for details. Table 13. EXT Register Assignments Banks 0-4 Bank0 EXT0 EXT1 EXT2 EXT3 EXT4 EXT5 EXT6 EXT7 User User User SPI Data Port0 Data Port2-Port1 Data A/D_Ch0 Data Interrupt status/ Bank Select Bank1 User User User User Port0 Data Port2-Port1 Data A/D_Ch1 Data Interrupt status/ Bank Select Bank2 User User User User User Port3 Data A/D_Ch2 Data Interrupt status/ Bank Select Bank3 User User User SPI Data User User A/D_Ch3 Data Interrupt status/ Bank Select Bank4 User User User User User User User Interrupt status/ Bank Select Table 14. EXT Register Assignments Banks 5-15 Bank5 EXT0 EXT1 EXT2 EXT3 EXT4 EXT5 EXT6 EXT7 A/D_Ch1 Data A/D_Ch2 Data A/D_Ch3 Data SPI Data Port0 Data Port2-Port1 Data A/D_Ch0 Data Interrupt status/ Bank Select Bank6-12 not defined not defined not defined not defined not defined not defined A/D_Ch0 Data Interrupt status/ Bank Select Bank13 A/D Control C/T0 Control C/T0 Load Bank14 C/T2 Load/Read C/T1 Control C/T1 Load Bank15 Port0 Control Port1 Ctrl/Port0 Alloc Ports 2, 3, & C/T2 Control C/T0 Counter C/T1 Counter Wait State Control C/T0 Prescaler Ld C/T1 Prescaler Ld SPI Control C/T0 Prescaler C/T1 Prescaler System Clock Control A/D_Ch0 Data Interrupt Polarity Interrupt Allocation Interrupt status/ Interrupt status/ Interrupt status/ Bank Select Bank Select Bank Select DS000202-DSP0599 29 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG BANK/EXT REGISTER ASSIGNMENTS (Continued) Interrupt Status/Bank Select RegisterNEXT7 Following is a description of EXT7. It contains both a Bank Select Field and Interrupt Status Bits. Bank Select Field. The four LSBs of EXT7 denote which Note: Write "1" to a particular status bit to clear that bit. Before exiting an interrupt service routine, the relevant interrupt bit(s) should be cleared. To clear a bit efficiently: * Load the value of EXT7 into a register or memory location * Then load that value back into EXT7 Performing these steps clear all of the interrupts that were pending, but leave the Register Bank Select unchanged. bank is selected as the current working bank. Interrupt Status Bits. These bits can be read to identify which interrupts are pending. A "1" denotes interrupt pending, and a "0" denotes no interrupt. This ability to identify interrupts is particularly useful in polled interrupt operation or when servicing ISR2, which may come from several sources. Ext 7 Reg D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Bank Select 0000 : Bank0 0001 : Bank1 : : 1111 : Bank15 Interrupt Status Bits Bit 4 = A/D Finish Interrupt Bit 5 = SPI Interrupt Bit 6 = Timer0 Interrupt Bit 7 = Timer1 Interrupt Bit 8 = Timer2 Interrupt Bit 9 = INT0 (H/W) Interrupt Bit 10 = INT1 (H/W) Interrupt Bit 11 = INT2 (H/W) Interrupt Reserved Figure 20. EXT7 Register 30 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter Interrupt Allocation RegisterNBank15/EXT6 Bits 3-0 of the Interrupt Allocation Register define which unique interrupt source the highest priority, and is allocated to ISR0 (Interrupt Service Request 0). Bits 7-4 of the Interrupt Allocation Register define which unique interrupt source has the second highest priority, and is allocated to ISR1 (Interrupt Service Request 1). Bits 15-8 of the Interrupt Allocation Register are enable bits for common interrupt sources which have the lowest priority, and are all allocated to ISR2 (Interrupt Service Request 2). All the enabled interrupts which are not allocated to ISR0 or ISR1, are allocated to ISR2. When an ISR2 interrupt occurs, the interrupt service routine must read the Interrupt Status Register in EXT7 to determine the source. The Interrupt Status Register can be used for polling interrupts. An Interrupt that is not selected as a source to ISR0, ISR1, or ISR2, is disabled. Bank 15/EXT6 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ISR0 Source (highest priority) 0000 = A/D 0001 = SPI 0010 = C/T0 0011 = C/T1 0100 = C/T2 0101 = INT0 0110 = INT1 0111 = INT2 1xxx = ISR0 Disabled ISR1 Source (medium priority) 0000 = A/D 0001 = SPI 0010 = C/T0 0011 = C/T1 0100 = C/T2 0101 = INT0 0110 = INT1 0111 = INT2 1xxx = ISR0 Disabled ISR2 Interrupt Source (lowest priority) 1 = Enable, 0 = Disable Bit 8 = A/D Bit 9 = SPI Bit 10 = C/T0 Bit 11 = C/T1 Bit 12 = C/T2 Bit 13 = INT0 Bit 14 = INT1 Bit 15 = INT2 Figure 21. Interrupt Allocation Register DS000202-DSP0599 31 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG BANK/EXT REGISTER ASSIGNMENTS (Continued) Interrupt Polarity RegisterNBank14/EXT6 The trigger polarities, rising-edge or falling-edge, of all the external interrupts are programmable. Bank 14/Ext 6 Reg D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 INT0 Polarity 0 : Rising Edge (default) 1 : Falling Edge INT1 Polarity 0 : Rising Edge (default) 1 : Falling Edge INT2 Polarity 0 : Rising Edge (default) 1 : Falling Edge Bits [15:3]--Reserved Figure 22. Interrupt Polarity Register Wait-State Control RegisterNBank15/EXT3 The Wait-State Control Register enables the insertion of wait states when the DSP accesses slow peripherals. This register enables the insertion of one wait state on the ED bus, providing 100 ns of access time instead of 50 ns when operating at 20 MHz. When more than one wait state is nec- essary, input pin P2.4/ WAIT can be used to provide additional wait states. The Wait-State Register enables the user to specify which EXT registers, EXT0-EXT6, and which operation, read and/or write, require a wait state. EXT7 is an internal register, and requires no wait state. Bank15/EXT3 Reg D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Wait-State EXT0 Wait-State EXT1 Wait-State EXT2 Wait-State EXT3 Wait-State EXT4 Wait-State EXT5 Wait-State EXT6 Bit14: 0 = Disabled WAIT Input Pin (default) 1 = Enabled P2.4 as WAIT Input Pin Bit 15: 0 = Disabled UO0, UO1 (default) 1 = Enable UO0, UO1 00 = read (nws), write (nws) 01 = read (nws), write (nws) 10 = read (ws), write (ws) 11 = read (ws), write (ws) nws = no wait state ws = one wait state Figure 23. Wait-State Control Register 32 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter I/O PORTS I/O pin allocation of ports for the different package types is designed to provide configuration flexibility. Each port line of Ports 0, 1, and 2 can be independently selected as an input or an output. Each port's output lines can be globally selected as push-pull or as open-drain outputs Table 15. I/O Port Bit Allocations Device Pins P0 MSB 44-Pin PLCC, 44-Pin PQFP ED15-ED8, or P0.15-P0.8, or P1.7-P1.0 ED7-ED0, or P0.7-P0.0 P2.4-P2.0 64-Pin TQFP, 68-Pin PLCC ED15-ED8, or P0.15-P0.8 ED7-ED0, or P0.7-P0.0 P1.7-P1.0 P2.7-P2.0 80-Pin PQFP ED15-ED8, or P0.15-P0.8 ED7-ED0, or P0.7-P0.0 P1.7-P1.0 P2.7-P2.0 P3.7-P3.0 P0 LSB P1 P2 P3 Open-Drain OEN PAD Data Out Data In Auto Latch R 500 k Figure 24. Port 0, 1 and 2 Configuration DS000202-DSP0599 33 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG I/O PORTS (Continued) Port0N16-Bit Programmable I/O Bank15/EXT0 is the Port0 direction control register. Bank15/EXT1 includes specific bits to enable and configure Port0. The Port0 data register is Ext4 in Banks 0, 1, or 5. Bank 15/Ext 0 Reg D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Port I/O Direction 0 = Input (default) 1 = Output Figure 25. Port 0 Control Register Bank 15/EXT1 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Allocation of External Data (ED) Bus/Port0 Pins 000 = ED Bus 15-0 (default) 001 = Pins 15-8 P1.7-P1.0, Pins 7-0 ED Bus 7-0 010 = Reserved 011 = Pins 15-8 P0.15-P08, Pins 7-0 ED Bus 7-0 100 = P0.15-P0.0 101 = Pins 15-8 P1.7-P1.0 Pins 7-0 P0.7-P0.0 110 = Reserved 111 = Reserved INT2 0 = Disabled (default) 1 = Enabled INT1 0 = Disabled (default) 1 = Enabled CLKOUT 0 = Disabled (default) 1 = Enabled Port1 Outputs 0 = Push-Pull (default) 1 = Open-Drain Port0 Outputs 0 = Push-Pull (default) 1 = Open-Drain Port I/O Output Bit Directions 0 = Input (default) 1 = Output Figure 26. Bank15/EXT1 Register 34 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter Port1N8-Bit Programmable I/O Bank15/EXT1 is the Port1 control register. The MSB is the Port1 direction control. Port1 data is accessed as the LSB of EXT5 in Banks 0, 1, or 5. The Port1 pins can also be mapped to internal functions. When INT2, CLKOUT, UI0 and UI1, or the SPI are enabled, they use Port1 pins. The 44-pin packages do not feature Port1 pins, however, Port1 and its internal functions can be mapped to the MSB of the ED Bus/Port0 pins. See bits 2-0 of Bank15/EXT1. Table 16. Port1 Bit Function Allocation Port Pin P1.0/INT2 P1.1/CLKOUT P1.2/SDI P1.3/SDO P1.4/SS P1.5/SCLK P1.6/UI0 P1.7/UI1 IF Bank15/EXT1 Bit 3 = 1 Bank15/EXT1 Bit 5 = 1 Bank15/EXT4 Bit 0 = 1 Bank15/EXT4 Bit 0 = 1 Bank15/EXT4 Bit 0 = 1 Bank15/EXT4 Bit 0 = 1 Bank13/EXT1 Bits [2,1] = 10, or Bank14/EXT1 Bits [2,1] = 10 Bank13/EXT1 Bits [2,1] = 11, or Bank14/EXT1 Bits [2,1] = 11 Condition Enable INT2 Enable CLKOUT Enable SPI Enable SPI Enable SPI Enable SPI Enable UI0 Enable UI1 Then INT2 CLKOUT SDI SDO SS SCLK UI0 UI1 Else P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 DS000202-DSP0599 35 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG I/O PORTS (Continued) Port2N8-Bit Programmable I/O Bank15/EXT2 is the Port2 control register. The LSB is the Port2 direction control. Port2 data is accessed as the MSB of EXT5 in Banks 0,1,or 5. The Port2 pins can also be mapped to internal functions. When INT0, INT1, TMO0, TMO1, WAIT, UI2, or TMO2 are enabled, they use Port2 pins. The 44-pin packages do not feature Port2 pins P2.7-P2.5. Table 17. Port2 Bit Function Allocation Port Pin P2.0/INT0 P2.1/INT1 P2.2/TMO0 P2.3/TMO1 P2.4/WAIT P2.5/UI2 P2.6/TMO2 P2.7 IF Bank15/EXT2 Bit 9 = 1 Bank15/EXT1 Bit 4 = 1 Bank13/EXT1 Bit [6,5] = 10, or Bank14/EXT1 Bit [6,5] = 10 Bank13/EXT1 Bit [6,5] = 11, or Bank14/EXT1 Bit [6,5] = 11 Bank15/EXT3 Bit 14 = 1 Bank15/EXT2 Bit 13 = 1 Bank15/EXT2 Bits 14 = 1 Condition Enable INT0 Enable INT1 Enable TMO0 Enable TMO1 Enable WAIT C/T2 clock is UI2 Enable TMO2 Then INT0 INT1 TMO0 TMO1 WAIT UI2 TMO2 P2.7 Else P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 Bank 15/EXT2 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Port2 I/O Directions 0 = Input (default) 1 = Output Port3 0 = Disabled (default) 1 = Enabled INT0 0 = Disabled (default) 1 = Enabled Port2 Outputs 0 = Push-Pull (default) 1 = Open-Drain Counter/Timer2 0 = Disabled (default) 1 = Enabled Counter/Timer2 Operation 0 = Stopped (default) 1 = Counting If D15 = 0, Counter/Timer2 Clock defined by 0 = System Clock/2 (default) 1 = UI2 If D15 = 1, Counter/Timer2 Sleep Mode Wake-Up 0 = Disabled (default) 1 = Enabled TMO2 0 = Disabled (default) 1 = Enabled Counter/Timer2 Clock 0 = Defined by D13 (default) 1 = CLKI Figure 27. Bank15/EXT2 Register 36 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter Port3N8-BIt Programmable I/O Port3 is an additional I/O port available only in the 80-pin package. P3.3-P3.0 are inputs and P3.7-P3.4 are outputs. Bit 8 of Bank15/EXT2 enables and disables Port3. The LSB of Bank2/EXT5 is the Port3 Data Register. DS000202-DSP0599 37 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG PERIPHERALS Analog to Digital Converter (A/D) The A/D is a 4-channel 8-bit half-flash converter. It uses two reference resistor ladders, one for the upper 5 bits, and another for the lower 3 bits. Two external reference voltage input pins, VAHI and VALO, set the input voltage measurement conversion range. The converter is auto-zeroed prior to each sampling period. Bank13/EXT0 is the A/D control register. The conversion time depends on the system clock frequency and the selection of the A/D prescaler value, bits DIV2-DIV0. The clock prescaler can be programmed to derive a 2 s conversion time. For example, when deriving the A/D clock from a 20-MHz system clock, the A/D prescaler value should be set to divide by 40. Bits ADST1-ADST0 determine one of the following start conversion options: * * * * Bits QUAD and SCAN determine one of the following Modes of operation: * * * * One channel is converted four times, with the results sequentially written to result registers 0, 1, 2 and 3. One channel is converted one time, with the respective result register updated. Four channels are converted one time each, with the respective four result registers updated. Four channels are converted repeatedly, with the respective four result registers constantly updated. When one of the two four-channel modes is selected, the channel specified by CSEL1-CSEL0 will convert first. The other three channels will convert in sequence. In the sequence, AN0 follows AN3. Bit ADIE enables the A/D to generate interrupts at the end of a conversion. Bit ADIT determines whether an interrupt occurs after the first or fourth conversion. To reduce power consumption the A/D can be disabled by clearing the ADE bit. Though the A/D will function with smaller input signals and reference voltages, the noise and offsets remain constant. The relative error of the converter will increase and the conversion time will also take longer. Writing to the ADCTL control register ISR1 C/T2 time-out C/T0 time-out The start conversion operation may begin at any time. If a conversion is in progress, and a new start conversion signal is received, the conversion in progress will abort, and a new conversion will initiate. ISR1 C/T0 C/T2 ADCTL Reg. Start Converter A/D Prescaler Channel Select Quad Scan A/D Control Register Internal Bus AN0 AN1 AN2 AN3 4-Channel Multiplexer Sample and Hold Half-Flash A/D Converter 4x8 Result Register Figure 28. ADC Architecture 38 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter Bank13/EXT0 (LSB) D7 D6 D5 D4 D3 D2 D1 D0 Bank13/EXT0 (MSB) D15 D14 D13 D12 D11 D10 D9 D8 CSEL0 CSEL1 (Reserved) SCAN QUAD DIV0 DIV1 DIV2 ADST0 ADST1 ADIE ADIT ADCINT (Reserved) ADE Figure 29. ADCTL Register (LSB) Table 18. A/D Prescaler Values (Bits 7, 6, 5) DIV2 0 0 0 0 1 1 1 1 DIV1 0 0 1 1 0 0 1 1 DIV0 0 1 0 1 0 1 0 1 A/D Prescaler (Crystal divided by) 8 16 24 32 40 48 56 64 Figure 30. ADCTL Register (MSB) ADE (Bit 15). A "0" disables any A/D conversions or ac- cessing any A/D registers, except writing to the ADE bit. A "1" enables all A/D accesses. Reserved (Bits 14, 13). Reserved for future use. ADCINT (Bit 12). The A/D interrupt bit is read-only. The ADCINT will reset every time this register is written. ADIT (Bit 11). Selects when to set the A/D interrupt if in- terrupts are enabled (ADIE=1). A value of "0" sets the interrupt after the first A/D conversion is complete. A value of "1" sets the interrupt after the fourth A/D conversion is complete. ADIE (Bit 10). A/D Interrupt Enable. A value of "0" dis- Table 19. Operating Modes (Bits 4, 3) QUAD 0 0 1 1 SCAN 0 1 0 1 Option Convert selected channel 4 times, then stop Convert selected channel, then stop. Convert 4 channels, then stop. Convert 4 channels continuously. ables the A/D Interrupt. A value of "1" enables the A/D Interrupt. Table 21. START (Bits 9, 8) ADST1 0 0 1 1 ADST0 0 1 0 1 Option Conversion starts when this register is written. Conversion starts on INT1 per Interrupt Allocation Register Conversion starts on C/T2 time-out. Conversion starts on C/T0 time-out. Table 20. Channel Select (Bits 1, 0) CSEL1 0 0 1 1 CSEL0 0 1 0 1 Channel AN0 AN1 AN2 AN3 There are four A/D result registers. See the EXT Register Assignments for their location in the different banks. DS000202-DSP0599 39 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG PERIPHERALS (Continued) Counter/Timers (C/T0 and C/T1) The Z893x3 features two 16-bit Counter/Timers (C/T) that can be independently configured to operate in various modes. Each is implemented as a 16-bit Load Register and a 16-bit down counter. Either C/T input can be selected from UI0 or UI1. Either C/T output can be directed to TMO0 or TMO1. The C/T clock is a scaled version of the system clock. Each C/T features an 8-bit prescaler. The clock rates of the two C/T are independent of each other. The C/Ts can be programmed to recognize clock events on the rising edge, the falling edge, or both rising and falling edges of the input signal. Outputs on TMO0 or TMO1 can be programmed to occur with either polarity. If either C/T is enabled and an output pin TMO0 or TMO1 is selected, and at the same time User Outputs are enabled, the C/T takes precedence, and Status Register bits 5 or 6 do not affect the state of the selected pin. C/T Modes of Operation: MODE 0--Square Wave Output. The C/T is configured from 0-100% (0/65,536 to 65,535/65,536; 16-bits) of a cycle in steps of 1/65,536 of a cycle. The asserted state of the waveform may be either logic High or logic Low. Writing a new pulse-width value to the TMLR Register takes effect at the end of current cycle, unless TMR is written. MODE 4--Finite Pulse String Generator. T h e C / T i s configured to generate 1 to 65,535 pulses. The output pulses are actually from the Timer Clock Prescaler divided by 2 (TMCLK). They are gated to the output until the Timer Down-Counter underflows. MODE 5--Externally Clocked One-Shot. T h e C / T i s configured to generate an output pulse. The pulse may be either logic High or logic Low. It is deasserted when a programmable number of input events (up to 65,535) occur on the input pin, UI0 or UI1. MODE 6--Software Watch-Dog Timer. The C/T is configured to generate a Hardware Reset on time-out, unless retriggered by software. MODE 7--Hardware Watch-Dog Timer. The C/T is configured to generate a Hardware Reset on time-out unless retriggered by an event on the input pin, UI0 or UI1. MODE 8--Pulse Stopwatch. The C/T is configured to measure the time during which its input is asserted. MODE 9--Edge-to-Edge Stopwatch. The C/T is configured to measure the period from one rising (falling) edge to the next rising (falling) edge on the input. MODE 10--Edge Counter. The C/T is configured to count a number of input edges (up to 65,535). Input edges may be selected as rising or falling or both. MODE 11--Gated Edge Counter. The C/T is configured to count the number of input edges (up to 65,535) in a time window set by the second timer. Edges are counted until the second timer underflows. Input edges may be selected as rising, falling, or both. to generate a continuous square wave of 50% duty cycle. Writing a new value to the TMLR Register takes effect at the end of the current cycle, unless TMR is written. MODE 1--Retriggerable One-Shot. The C/T is config- ured to generate a single pulse of programmable duration. The pulse may be either logic High or logic Low. Retriggering the one-shot before the end of the pulse causes it to retrigger for a new duration. MODE 2--8-Bit PWM. The C/T is configured to generate a pulse-width modulated waveform. The duty cycle ranges from 0-100% (0/256 to 255/256; 8-bits) of a cycle in steps of 1/256 of a cycle. The asserted state of the waveform may be either logic High or logic Low. Writing a new pulsewidth value to the TMLR Register takes effect at the end of current cycle, unless TMR is written. MODE 3--16-Bit PWM. The C/T is configured to generate a pulse-width modulated waveform. The duty cycle ranges UI1 UI0 15 1 Zeros 87 TPLR 0 15 Timer Load Register MUX 80h TPR System Clock 8-Bit Counter /2 15 16-Bit Down Counter TMR 0 MUX TMLR 0 Prescaler Value TMCLKIN = System Clock 2 x (TPR + 1) TMCLKOUT = TMCLK (TMR + 1) Figure 31. Counter/Timer 0 and 1 Block Diagram 40 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter Bank 13/EXT1 (C/T0) and Bank14/EXT1 (C/T1) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C/T 0 = Disabled (default) 1 = Enabled Input Select 00 = Inputs have no effect (default) 01 = Reserved 10 = UI0 Pin 11 = UI1 Pin Input Event 00 = Falling Edge (default) 01 = Rising Edge 10 = Both Rising and Falling Edges 11 = Reserved Output Select 00 = Outputs Unaffected (default) 01 = Reserved 10 = Drive TMO0 Pin 11 = Reserved Output Polarity 0 = Output asserted High on Timeout (default) 1 = Output asserted Low on Timeout Mode of Operation 0000 = Square Wave Output (default) 0001 = Retriggerable One-Shot 0010 = PWM (8-bit) 0011 = PWM (16-bit) 0100 = Finite Pulse String Generator 0101 = Externally-Clocked One-Shot 0110 = Software Watch-Dog Timer 0111 = Hardware Watch-Dog Timer 1000 = Pulse Stopwatch 1001 = Edge-to-edge Stopwatch 1010 = Edge Counter 1011 = Gated Edge Counter Reserved Test Mode* 0 = Normal Operation 1 = Factory Test Mode *Note: The user should always program this bit to "0". Figure 32. C/T0 and C/T1 Control Register C/T Registers Each C/T contains a set of five 16-bit Registers. Bank13 is used to access the registers for C/T0 and Bank14 is for the C/T1 registers. All accesses to C/T Registers occur with zero wait states. Counter/Timer Control Register (Bank13,14/EXT1). The C/T Control register enables/disables the C/T, selects input and output options, and the mode of operation. TMLR--Load Register (Bank13,14/EXT2). T h e 1 6 - b i t to TMR is different than writing to an ordinary register. A write to TMR causes the contents of TMLR to be written into TMR, causing the C/T to be retriggered. TPLR--Prescaler Load Register (Bank13,14/EXT4). T h e 16-bit TPLR register holds the prescaler load value in its lower 8 bits. Bit 15 must be written with a "1", and bits 14-8 must be written with "0's". Note: If the C/T interrupt is being used, this register must be rewritten at the end of the interrupt service routine in order to enable the next interrupt. The number of clock cycles from the beginning of the interrupt service routine to the write must exceed the prescaler load value. TMLR register holds the value that is loaded into TMR when TMR underflows. TMR--Counter Register (Bank13,14/EXT3). TMR is a 16-bit down counter that holds the current C/T value. It can be read like any other ordinary register. However, writing DS000202-DSP0599 41 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG PERIPHERALS (Continued) TPR--Prescaler Register (Bank13,14/EXT5). TPR is an 8-bit down counter that holds the current Prescaler Count Value. It can be read like any other ordinary register. However, writing to TPR is different than writing to an ordinary register. A write to TPR causes the lower 8-bit contents of TPLR to be written into TPR, causing the Prescaler to be retriggered. 15 Bank 13,14/EXT2 Timer Reload Value 0 7 Bank 13,14/EXT5 TPR 8-Bit Counter 0 Figure 36. TPR--Prescaler Register Prescaler Operation The Prescaler section comprises TPLR and TPR, followed by a divide-by-two flip-flop. This operation generates a 50 percent duty cycle output, TMCLKIN. TPR's input clock is the system clock. The maximum prescaler output frequency is 1/2 the system clock frequency. Figure 33. TMLR--Load Register 15 Bank 13,14/EXT3 Timer Register 0 After TPR is loaded, it decrements at the system clock frequency and generates an output to the divide-by-two flipflop. When the count reaches 0, the TPR counter is reloaded from the lower 8 bits of TPLR Register. Two other events cause a reloading of the TPR counter: 1. Writing to TPR 2. Reloading TMR, which happens when TMR underflows, or when TMR is written. Figure 34. TMR--Counter Register 15 O1O 14 Bank 13,14/EXT4 87 Zeros Prescaler Reload Value 0 Note: For C/T Modes 8-11, the external input signal on UI0 or UI1 is synchronized with TMCLKIN before being applied to TMR. The external input signal frequency must be no higher than 1/2 of the TMCLKIN frequency. Figure 35. TPLR--Prescaler Load Register 42 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter GENERAL-PURPOSE COUNTER/TIMER (C/T2) This versatile16-bit C/T offers multiple uses, including Sleep Mode Wake-up. It can be clocked with the slow 32 kHz crystal clock (CLKI), while the DSP and other peripheral functions operate at a higher frequency generated by the PLL. Also included is an independent long duration timer. GPT is a 16-bit down counter that holds the current C/T value. It can be read like any other ordinary register. GPTL and GPT share the same address, Bank14/EXT0. A write to GPTL reloads GPT, causing the C/T to be retriggered. When C/T2 underflows, it is reloaded with the most recent value written to GPTL. If the C/T2 interrupt is enabled, at underflow an interrupt is generated. The counting operation of the counter can be disabled. The C/T clock source can be selected to be CLKI, UI2, or the system clock divided by 2. When the C/T2 output is enabled, it drives the TMO2 pin. Bank 15/EXT2 is the control register for C/T2, and for I/O Ports 2 and 3. Refer to the I/O Ports section, page 33, for a description of the I/O port bit allocation. Table 22. C/T2 Bits D15 and D13 D15 0 0 1 1 D13 0 1 0 1 C/T2 Clock SYSCLK / 2 (default) UI2 CLKI CLKI Sleep/Wake-Up Mode n/a n/a Disabled Enabled 15 CLKI UI2 System Clock /2 MUX GPTL-Bank14/EXT0 Write Timer Load Register 0 15 16-Bit Down Counter TMR 0 MUX TMO2 Sleep Mode Wake-Up GPT-Bank14/EXT0 (Read) Figure 37. Counter/Timer2 Block Diagram DS000202-DSP0599 43 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG GENERAL-PURPOSE COUNTER/TIMER (C/T2) (Continued) Bank 15/EXT2 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Port2 I/O Directions 0 = Input (default) 1 = Output Port3 0 = Disabled (default) 1 = Enabled INT0 0 = Disabled (default) 1 = Enabled Port2 Outputs 0 = Push-Pull (default) 1 = Open-Drain Counter/Timer2 0 = Disabled (default) 1 = Enabled Counter/Timer2 Operation 0 = Stopped (default) 1 = Counting If D15 = 0, Counter/Timer2 Clock defined by 0 = System Clock/2 (default) 1 = UI2 If D15 = 1, Counter/Timer2 Sleep Mode Wake-Up 0 = Disabled (default) 1 = Enabled TMO2 0 = Disabled (default) 1 = Enabled Counter/Timer2 Clock 0 = Defined by D13 (default) 1 = CLKI Figure 38. Counter/Timer2 Control Register 44 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter SERIAL PERIPHERAL INTERFACE The Z893x3 incorporates a Serial Peripheral Interface (SPI) for communication with other microcontrollers and peripherals. The SPI can be operated either as the system Master, or as a system Slave. The SPI consists of three registers: the SPI Control Register (Bank15/EXT4), the SPI Receive/Buffer Register (RxBUF), and the SPI Shift Register. SPI Control Register This register is the Low byte of Bank15/EXT4. It is a read/write register that controls Master/Slave selection, SS polarity, clock source and phase selection, and indicates byte available and data overrun conditions. The control register is multifunction depending on Master/Slave mode selection. In Master mode, Bit 6 defines the SPI clock source. A "1" selects SCLK = C/T0 output, and a "0" selects SCLK = System Clock divided down by 2, 4, 8, or 16, as determined by bits 1 and 2. In Slave Mode, bit 1 is the Receive Byte Overrun flag. This flag can be cleared by writing a "0" to this bit. Bit 2 is the SDO output enable.A "0" tristates SDO, a "1" enables data output on SDO. Bit 4 signals that a receive byte is available in the RxBUF Register. If the associated interrupt enable bit is enabled, an interrupt is generated. SPI Data Access Receive operations are double buffered. Bank0/EXT3 accesses both RxBUF for read (receive) operations, and the SPI shift register for write (transmit) operations. Bank 0/EXT 3 Register D15 D14 D7 D6 D5 D4 D3 D2 D1 D0 Bits 70 SPI Data (SPI Shift Register for transmit and RxBUF for receive) Bit 14 Receive Character Available Bit 15 Receive Character Overrun Figure 39. SPI Data Access Bank15/EXT4 (LSB) D7 D6 D5 D4 D3 D2 D1 D0 Mode of Operation 0 = Slave 1 = Master SPI Clock Source Select (Master) 0 = System Clock divided down. 1 = C/T0 SCLK Polarity 0 = Transmit on Falling Edge, Receive on Rising Edge 1 = Transmit on Rising Edge, Receive on Falling Edge SPI Enable 0 = Disable (default) 1 = Enable Receive Byte Overrun (Slave) Output Enable(Slave) 0 = Tri-State SDO 1 = Enable SDO as Output SCLK Frequency (Master) 00 = System Clock /2 01 = System Clock /4 10 = System Clock /8 11 = System Clock /16 Slave Select Polarity 0 = SS Active Low (default) 1 = SS Active High Received Byte Available Figure 40. SPI Control Register Master Mode Operation The DSP must first activate the target slave's select pin through an I/O port. Loading data into the SPI Shift Register initiates the transfer. Data is transferred out the SDO pin to the slave one data bit per SCLK cycle. The MSB is shifted out first. At the conclusion of the transfer, the Receive Byte Available flag is set, and if enabled, an SPI interrupt is generated. The Receive Byte Available flag is reset when RxBUF is read. DS000202-DSP0599 45 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG SERIAL PERIPHERAL INTERFACE (Continued) Slave Mode Operation SS must be asserted to enable a data transfer. Incoming data on the SDI pin is shifted into the SPI Shift Register one data bit per SCLK cycle. When a byte of data is received, the SPI Shift Register contents are automatically copied into RxBUF. The Receive Byte Available flag is set, and if enabled, an SPI interrupt is generated. The next byte of data may be received at this time. The current byte in RxBUF must be read before the next byte's reception is complete, or the Receive Byte Overrun flag will set, and the data in RxBUF will be overwritten. The Receive Byte Available flag is reset when RxBUF is read. Unless the SPI output, SDO, is disabled, for every bit that is transferred into the slave through the SDI pin, a bit is transferred out through the SDO pin on the opposite clock edge. During slave operation, SCLK is an input. Note: Slave Mode is not available on the 44-pin package. C/T0 System Clock (from PLL Block) SCLK/P1.5 SPI Clock SPI* I/O SPI Shift Register SDO/P1.3 SDI/P1.2 SS/P1.4 SPI Counter Interrupt SPI Receive Buffer (RxBuf) SPI Control (SCON) INT Figure 41. SPI Block Diagram 46 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter SYSTEM CLOCK GENERATOR The System Clock can be generated from an external clock signal, or from the internal crystal oscillator. For the latter case, a 32-kHz crystal is used in conjunction with the internal crystal oscillator. The system clock generator includes a Phase-Locked Loop (PLL) circuit to derive a highfrequency System Clock from the low-frequency crystal oscillator. The benefits of using a low-frequency crystal are Off-Chip LPF On-Chip lower system cost, lower power consumption and lower EMI. The Z893x3 supports several low-power clock modes to optimize power consumption. Total power consumption depends on System Clock frequency, and which oscillators and peripherals are enabled. PLL LPF Phase Detector /2 8-Bit Clock Divide VCO VCO Out /2 01 /2 10 11 PLL In System Clock Select PLL Out. Sel. Clock Stop VCO Control PLL Divisor Register Stop XTAL Osc MUX PLL Out CLKI 1 System Clock MUX 0 00 CLKI 32 kHz CLKO XTAL Osc. Figure 42. System Clock Generator Modes of Operation The various modes of clock operation are selected by writing to the appropriate bits and fields of the Clock Control Register, Bank15/EXT5. The mode of operation can be switched dynamically during program execution. Power-up and Reset (Default) Crystal Oscillator DIrect At power-up, and following a reset or Sleep Mode Recovery, System Clock Select = 0, therefore system clock = CLKI. The XTAL Oscillator is running, so CLKI may be provided by a crystal, as depicted, or by an external clock (not shown). The VCO is running to minimize the time required to switch the system clock to PLL Out. External Clock Direct In this mode of operation, the XTAL Oscillator is running, and an external crystal provides a 32-kHz (typical) clock at CLKI. System Clock Select = 0, so the System Clock is the frequency at CLKI (32 kHz). This mode requires less power than running at a high-frequency clock rate. The VCO may be stopped to conserve even more power, or left running for rapid switching (wake up) to a high-frequency PLL generated clock. Whenever the PLL circuit is enabled, Stop VCO = 0, and a software delay of 10 ms must be observed before switching System Clock from CLKI to PLL Out. As a result, the PLL has time to stabilize. PLL Clock In this mode, an external clock on CLKI provides the System Clock. CLKO is not connected. System Clock Select = 0. The PLL is not used. The XTAL oscillator and VCO are both stopped to reduce power consumption. An external 32-kHz crystal, together with the on-chip XTAL oscillator, provides the PLL input. The VCO generates the System Clock. A low-pass filter must be connected to LPF as depicted. The XTAL oscillator and VCO are both running, and System Clock = PLL Out (System Clock Select = 1). The frequency generated by the PLL is deter- DS000202-DSP0599 47 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG SYSTEM CLOCK GENERATOR (Continued) mined by the PLL Divisor value in the MSB of the Clock Control Register, Bank15/EXT5: VCO Frequency = 4 x PLL Divisor x PLL In Frequency. The PLL Divisor value should be between 1 and156 to obtain a VCO Frequency between 128 kHz and 20 MHz from a 32-kHz input. There are four options for PLL Out: VCO Out, VCO Out divided by 2, VCO Out divided by four, or twice the crystal frequency. This selection is determined by the PLL Out Select bits in the Clock Control Register. Note: The PLL is designed and tested to operate with an input frequency of approximately 32 kHz. It is possible to drive the input with a crystal or user-generated clock at some other frequency, but the results are not guaranteed. Sleep Modes Mode Power-up/Reset (default) PLL Clock Crystal Oscillator Direct External Clock Direct Deep Sleep (lowest power) Table 23. Standard Clock Mode Summary CLKI Src XTAL, User XTAL XTAL User XTAL, User Stop XTAL Osc. 0 0 0 1 1 Stop VCO 0 0 1 1 1 Sys Clk Sel 0 1 0 0 1 Wake-Up From Sleep Modes The Z893x3 supports various Clock Modes to minimize device power consumption. The lowest power mode is Deep Sleep in which the System Clock is stopped, and the VCO and XTAL Oscillator are both turned off. The Wake-up Trigger Source is specified by bits 5 and 6 of the Clock Control Register. The polarity of the Wakeup signal is defined by bit 7. Wake-up occurs when the wake-up signal is toggled to the specified wake-up polarity. Wake-up resumes operation starting from the reset vector address in the same way the chip responds to an external RESET. Bank 15/Ext 5 Reg D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 STOP_OSC 0 : Oscillator Running 1 : Stop Oscillator STOP_VCO 0 : VCO Running 1 : Stop VCO BYPASS_PLL 0 : Clock Source is Oscillator 1 : Clock Source is VCO DSP (System) Clock Source 00 : VCO Clock 01 : VCO Clock Divided by 2 10 : VCO Clock Divided by 4 11 : Twice the Crystal Frequency Recovery Source 00 : POR (Power-On Reset) or Port 2, Bit 0 (INT0) 01 : POR or Port 1, Bit 4 (SS) 10 : POR or Port 1, Bit 6 (UI0) 11 : POR or Port 2, Bit 0 or Port 1, Bit 4 or Port 1, Bit 6 STOP Recovery Level 0 : Low (Default setting after reset) 1 : High Programmable PLL Divider Register System Clock = Bits 158 x 4 x Crystal Frequency (32.768 kHz) Figure 43. System Clock Control Register 48 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter INSTRUCTION SET The addressing modes are: dresses in each bank of RAM. The 4-bit address comes from 2 bits of the status register and 2 bits of the operand field of the data pointer. Data registers can be used to access data in RAM, but typically are used as pointers to access data from the program memory. program memory read is stored in the Accumulator. Hence, @A in the second operand field loads the number in memory specified by the address in A. program memory. The address of the memory is located in a RAM location, which is specified by the value in a pointer. Therefore, @@P1:1 instructs the processor to read from a location in memory, which is specified by a value in RAM, and the location of the RAM is in turn specified by the value in the pointer. Note: the data pointer can also be used for a memory access in this manner, but only one "@" precedes the pointer. In both cases, each time the addressing mode is used, the memory address stored in RAM is incremented by one to allow easy transfer of sequential data from program memory. from the Accumulator by specifying the absolute address of the RAM in the operand of the instruction. A number between 0 and 255 indicates a location in RAM bank 0, and a number between 256 and 511 indicates a location in RAM bank 1. Table 24. Instruction Set Addressing Modes Symbolic Name DS000202-DSP0599 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG CONDITION CODES The following Instruction Description defines the condition codes supported by the DSP assembler. If the instruction description refers to the Code C EQ F IE MI NC NE NIE NOV NU0 NU1 NZ OV PL U0 U1 UGE ULT Z Description Carry Equal (same as Z) False Interrupts Enabled Minus No Carry Not Equal (same as NZ) Not Interrupts Enabled Not Overflow Not User Zero Not User One Not zero Overflow Plus (Positive) User Zero User One Unsigned Greater Than or Equal (Same as NC) Unsigned Less Than (Same as C) Zero 50 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter INSTRUCTION DESCRIPTIONS Inst. ABS ADD Description Absolute Value Addition Synopsis ABS[ AND CALL CCF CIEF COPF CP DEC INC JP DS000202-DSP0599 51 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG INSTRUCTION DESCRIPTIONS (Continued) Inst. LD Description Load destination with source Synopsis LD Notes: When 52 DS000202-DSP0599 ZiLOG Inst. Description Synopsis Operands Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter Words Cycles Examples Notes: If src1 is DS000202-DSP0599 53 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG INSTRUCTION DESCRIPTIONS (Continued) Inst. XOR Description Synopsis Operands A, Bitwise XOR Bank Switch Operand. The third (optional) operand of the MLD, MPYA and MPYS instructions represents whether the bank switch is set to ON or OFF. To illustrate, the keywords ON and OFF are used to state the direction of the switch. These keywords are referenced in the instruction descriptions through the 54 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter PACKAGE INFORMATION Figure 44. 44-Pin PLCC Package Diagram Figure 45. 44-Pin PQFP Package Diagram DS000202-DSP0599 55 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG PACKAGE INFORMATION (Continued) Figure 46. 64-Pin TQFP Package Diagram 56 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter Figure 47. 68-Pin PLCC Package Diagram DS000202-DSP0599 57 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG PACKAGE INFORMATION (Continued) Figure 48. 80-Pin PQFP Package Diagram 58 DS000202-DSP0599 ZiLOG Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ORDERING INFORMATION Package Type 44-Pin PLCC 44-Pin PQFP 64-Pin TQFP 68-Pin PLCC 80-Pin PQFP ROM Z8922320VSC Z8922320VEC Z8922320FSC Z8922320FEC Z8932320ASC Z8932320AEC Z8932320VSC Z8932320VEC Z8932320FSC Z8932320FEC OTP Z8927320VSC Z8937320ASC Z8937320VSC Z8937320FSC For fast results, contact your local ZiLOG sales office for assistance in ordering the part required. CODES Package V = PLCC A = TQFP F = PQFP S = 0C to +70C E = -40C to 85C 20 = 20 MHz C = Plastic Standard Temperature Speed Environmental Example: Z 89323 20 V S C is a Z89323, 20 MHz, PLCC, 0C to +70C, Plastic Standard Flow Environmental Flow Temperature Package Speed/Bond Out Option Product Number ZiLOG Prefix DS000202-DSP0599 59 Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ZiLOG (c)1999 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights. ZiLOG, Inc. 910 East Hamilton Avenue, Suite 110 Campbell, CA 95008 Telephone (408) 558-8500 FAX (408) 558-8300 Internet: http://www.zilog.com DS000202-DSP0599 60 |
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